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硬件設計
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拳皇98ol魂匣: 1.     Introduction

This document describes the hardware required to implement the requirement specified in PROJECTXXX Product Specification
This document is mainly composed with 6 parts:
a. PCI-E switch parts - Consists of PEX8712/13 PLX PCI-E switch, with Power/clk/reset etc design notes.
b. Marvell 88E1111 - Consists of Marvell 88E1111 design notes.
c. Clock and Reset Distribution – introduce Clock and reset design notes under system level
d. DDR3 - Consists of DDR3 circuit.
e. APB bus design notes – APB bus design notes.
f. LED indication – to indicates system running status.
The PROJECTXXX ports Switch System block diagram is shown below





                                                           Figure 1.1 –PROJECTXXX Switch Block Diagram

2.     PCI-E Switch pex8712/pex8713 parts

PCI-E switch PEX8712/8713 block diagram is shown below, they can pin to pin compatible, so if PEX8713 is out of stock, we can use PEX8712 to replace PEX8713 in the products

             Figure 2.1- PCI-E switch configuration

2.1                Overview

The PEX 8713 is well-suited for fan-in/out applications, as well as for applications requiring peer-topeer
communication. The PEX 8713 supports two functional modes – Base and Virtual Switch:
? Base mode – PEX 8713 acts as a standard PCI Express switch, supporting one Host hierarchy
? Virtual Switch mode – PEX 8713 supports up to two Hosts, creating up to two virtual switches
within the PEX 8713, each with its own virtual hierarchy

                          Figure 2.2- PCI-E function overview

2.1                Port Configure Method

Use PLX Chip port configuration method

 
1-       Use Hardware pin, strap_stn0_portcfg[1..0] to configure the relative switch to 3 x4 port.
Hardware design, use the pull up or pull down resistor.
2-       Use EEPROM to configure the chip.
We can change EEPROM value to change the 300h register to change the port configuration.
3-       Use I2C to configure the chip. => by USB dongle, PLX debug tool.
We can use this method to change port configuration, then can be easily cooperated with the system.

 

2.1                Upstream Port/Downstream Port Selection/Change method

1-       Use Hardware pin, STRAP_UPSTRM_PORT_SEL[2:0] to change the upstream port
2-       Use EEPROM to change the Upstream port, register:360h
3-       Use I2C interface to configure the chip,=> by USB dongle, PLX debug tool.
We can use this method to change the upstream port and downstream, then can be easily cooperated with system

2.2                PCI-E Eye Measurement

For Gen3 parts, the serdes eye is much cleaner with both the width and height information being made available to the user, we can use this method to double check the PCI-E Lane Eye, intead of oscilloscope.


The eye requirement for the 5Gbps is shown below. All the test result must pass the eye height and width to gvrantee the signal integration.


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